Formal Methods in Specification and Synthesis of Petri net based Reprogrammable Logic Controllers

The goal of the paper is to present a novel approach to Application Specific Logic Controllers realisations, which is suitable especially for small, embedded system designs. A discrete model of a Logic Controller is derived directly from Control Interpreted Petri Net or related Sequential Function Chart (SFC), and synthesised as a dedicated microsystem. The unified, formal intermediate model is reflected in Programmable Logic (CPLD or FPGA), by means of the direct mapping of logic conditional expressions (declarative rules) in programmable hardware. The desired behaviour of the designed logic controller can be validated by simulation in VHDL environment. The Reprogrammable (Reconfigurable) Logic Controller is implemented from VHDL textual front-end entry.